Filler Cells and Decap Cells

Filler Cells:

Filling 100% of the area with regular cells are generally impossible. We need spaces to improve the placement and routing. Once we complete the routing & achieve the timing closure, we may need to fill the empty spaces with filler cells for the following purpose.

• To reduce the DRC Violations created by the base(NWell, PPlus & NPlus) layers.

• Power Rail connection continuity.

Filler Cells doesn't have functionality. They have power rails, Nwell, PPlus and NPlus layers only. If we want to do any ECO's, then the filler cells can be deleted and the empty spaces can be utilized.

Decap Cells:

Clock Latency and Clock Uncertainty

Clock Latency:

• It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin.
• This is a delay specified by the user - not a real, measured thing.

Clock Uncertainty:

In ideal mode the clock signal can arrive at all clock pins simultaneously, but in real world that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty.

For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.

A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:

• The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
  

• The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.

• Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

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Spare Cells

Spare Cells:

• Spare cells are nothing but the Standard Cells.
  
• These cells are placed randomly across the chip for later use.
• Whenever we need to perform some functional ECO's, the spare cells will be used.
• If any bugs reported after the tape-out, we can use these spare cells to fix the bugs.
• The key in having spare cells in your design is that you only need to change the metal layers in order to rewire the logic and fix any bugs. This means you only need to pay for new metal masks, thus SAVING MONEY.
  
• It is basically reduces the cost required to prepare the masks during fabrication as only we need to change the metal layers.
• After a 1.0 tape-out, a 1.1 tape-out means you only changed some metal layers while 2.0 tape-out means you changed your base layers as well.
• These cells can be added by both RTL Designer and Physical Design Engineer based on their project requirement.
• The Spare Cell Input pins must be tied to VSS and Output pins left floating.
  

Please have a look at the following page for more info on spare cells.

http://asicdigitaldesign.wordpress.com/2007/11/26/spare-cells

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