Timing Analysis - Part 2

What is Dynamic Timing Analysis?.

Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulation vectors cannot guarantee the 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Advantages:

• More Accurate than Static Timing Analysis.
• Uses the same test stimulus as Logic Simulation.
• Evaluates worst-case timing using both minimum and maximum delay.
  
• Best Method to Analyze the Asynchronous Circuits.
• Does not report false errors.
  

Limitations:

• Requires an exhaustive set of input test vectors.
• It is not path oriented.
  
• Slow when compared to STA as it checks the functionality of the design.
• It requires functional behavioral models.
  
• Requires more memory and CPU resources than STA.

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Timing Analysis - Part 1

What is Static Timing Analysis?.

There are so many definitions available for Static Timing Analysis and I have captured few of them below.

• Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.

• Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

• STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

Advantages:

• It is path oriented and finds all setup and hold violations.
• Much faster than timing-driven and gate-level Simulation.
• Exhaustive in nature.
• Circuit functionality is not checked.
• Does not required any input vectors for the analysis.

Limitations:

• Works best with Synchronous circuits.
• Complex to learn.
  
• Must define timing requirements and exceptions.
• It can report false errors.
• It cannot detect timing errors related to logical operation.
  
• Difficulty in handling with Multiple Clocks, False Paths, Latches and Multicycle Paths.