Timing Analysis - Part 1

What is Static Timing Analysis?.

There are so many definitions available for Static Timing Analysis and I have captured few of them below.

• Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.

• Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

• STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

Advantages:

• It is path oriented and finds all setup and hold violations.
• Much faster than timing-driven and gate-level Simulation.
• Exhaustive in nature.
• Circuit functionality is not checked.
• Does not required any input vectors for the analysis.

Limitations:

• Works best with Synchronous circuits.
• Complex to learn.
  
• Must define timing requirements and exceptions.
• It can report false errors.
• It cannot detect timing errors related to logical operation.
  
• Difficulty in handling with Multiple Clocks, False Paths, Latches and Multicycle Paths.