Timing Analysis - Part 4

Some more commonly used terms in Timing Analysis.

False Path:

• False paths are paths in a design which are functionally never be true.
• A path which has no functional purpose or a path which does not need to be timing constrained.
  
• Paths that are physically exists in the design, but they are not logical/functional paths. These paths are never get sensitized under any input conditions.

Example :

There are 4 timing paths present in the above circuit. They are

• Path 1 -> (A-C-C1-C2-Out)
• Path 2 -> (A-C-Out)
  
• Path 3 -> (B-B1-B2-C-C1-C2-Out)
  
• Path 4 -> (B-B1-B2-C-Out)

Only Path 1 and Path 4 in the above are valid logic paths as select line for the 2 muxes are the same.

MultiCycle Path:

• Multicycle paths are paths which intentionally require more than one clock cycle to propagate the data.

Divided Clock:

• A Clock divider circuit generates a new clock signal with a lower frequency than the original clock signal.

Gated Clock:

• A Gated Clock signal occurs when the clock network contains logic other than inverters and buffers.