Timing Analysis - Part 5

Data Path Types:

The first step for performing Timing Analysis is to break the design into a set of Timing Paths. Each Path has a start-point and end-point.

• The start-point of a path is a clock pin of a sequential element or possibly an input port of the design (The input data can be launched from some external source ).
  

• The end-point of a path is a data input of a sequential element or possibly an output port of the design (The output data can be captured by some external work).
  

The data paths can be divided into 4 types.

• Primary Input - to - Register Path.

• Register - to - Register Path.

• Register - to - Primary Output Path.

• Primary Input - to - Primary Output Path.

Primary Input - to - Register Path:

• Delays off-chip + Combinational logic delays up to the first sequential device.

Register - to - Register Path:

• Delay and timing constraint(Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times.

Register - to - Primary Output Path:

• Starts at a Sequential device.

• CLK-to-Q transition delay + Combinational logic delay + external delay requirements.

Primary Input - to - Primary Output Path:

• Delays off-chip + Combinational logic delays + external delay requirements.

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