Spare Cells

Spare Cells:

• Spare cells are nothing but the Standard Cells.
  
• These cells are placed randomly across the chip for later use.
• Whenever we need to perform some functional ECO's, the spare cells will be used.
• If any bugs reported after the tape-out, we can use these spare cells to fix the bugs.
• The key in having spare cells in your design is that you only need to change the metal layers in order to rewire the logic and fix any bugs. This means you only need to pay for new metal masks, thus SAVING MONEY.
  
• It is basically reduces the cost required to prepare the masks during fabrication as only we need to change the metal layers.
• After a 1.0 tape-out, a 1.1 tape-out means you only changed some metal layers while 2.0 tape-out means you changed your base layers as well.
• These cells can be added by both RTL Designer and Physical Design Engineer based on their project requirement.
• The Spare Cell Input pins must be tied to VSS and Output pins left floating.
  

Please have a look at the following page for more info on spare cells.

http://asicdigitaldesign.wordpress.com/2007/11/26/spare-cells

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