Clock Latency and Clock Uncertainty

Clock Latency:

• It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin.
• This is a delay specified by the user - not a real, measured thing.

Clock Uncertainty:

In ideal mode the clock signal can arrive at all clock pins simultaneously, but in real world that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty.

For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.

A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:

• The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
  

• The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.

• Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

.