How to Read SPEF?

SPEF (Standard Parasitic Exchange Format) is documented in chapter 9 of IEEE 1481-1999. Several methods of describing parasitics are documented, but we are discussing only few important one.

General Syntax

A typical SPEF file will have 4 main sections

– a header section,

– a name map section,

– a top level port section and

– the main parasitic description section.

Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP and *D_NET.

Comments start anywhere on a line with // and run to the end of the line. Each line in a block of comments must start with //.

Header Information

The header section is 14 lines containing information about

– the design name,

– the parasitic extraction tool,

– naming styles

– and units.

When reading SPEF, it is important to check the header for units as they vary across tools. By default, SPEF from Astro will be in pF and kOhm while SPEF from Star-RCXT will be in fF and Ohm.

Name Map Section

To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded by a *. This mapping is defined in the name map section. For example:

*NAME_MAP

*509 F_C_EP2

*510 F_C_EP3

*511 F_C_EP4

*512 F_C_EP5

*513 TOP/BUF_ZCLK_2_pin_Z_1

*514 TOP/BUF_ZCLK_3_pin_Z_1

*515 TOP/BUF_ZCLK_4_pin_Z_1

Later in the file, F_C_EP2 can be referred to by its name or by *509. Name mapping in SPEF is not required. Also, mapped and non-mapped names can appear in the same file. Typically, short names such as a pin named A will not be mapped as mapping would not reduce file size. You can write a script will map the numbers back into names. This will make SPEF easier to read, but greatly increase file size.

Port Section

The port section is simply a list of the top level ports in a design. They are also annotated as input, output or bidirect with an I, O or B. For example:

*PORTS

*1 I

*2 I

*3 O

*4 O

*5 O

*6 O

*7 O

*8 B

*9 B

Parasitics

Each extracted net will have a *D_NET section. This will usually consist of a *D_NET line, a *CONN section, a *CAP section, *RES section and a *END line. Single pin nets will not have a *RES section. Nets connected by abutting pins will not have a *CAP section.

*D_NET regcontrol_top/GRC/n13345 1.94482

*CONN

*I regcontrol_top/GRC/U9743:E I *C 537.855 9150.11 *L 3.70000

*I regcontrol_top/GRC/U9409:A I *C 540.735 9146.02 *L 5.40000

*I regcontrol_top/GRC/U9407:Z O *C 549.370 9149.88 *D OR2M1P

*CAP

1 regcontrol_top/GRC/U9743:E 0.936057

2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675

3 regcontrol_top/GRC/U9407:Z 0.386093

*RES

1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916

2 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9409:A 8.07710

3 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U9407:Z 11.9156

*END

The *D_NET line tells the net name and the net's total capacitance. This capacitance will be the sum of all the capacitances in the *CAP section.

*CONN Section

The *CONN section lists the pins connected to the net. A connection to a cell instance starts with a *I. A connection to a top level port starts with a *P.

The syntax of the *CONN entries is:

*I *C

Where:

– The pin name is the name of the pin.

– The direction will be I, O or B for input, output or bidirect.

– The xy coordinate will be the location of the pin in the layout.

– For an input, the loading information will be *L and the pin's capacitance.

– For an output, the driving information will be *D and the driving cell's type.

– Coordinates for *P port entries may not be accurate because some extraction tools look for the physical location of the logical port (which does not exist) rather then the location of the corresponding pin.

*CAP Section

The *CAP section provides detailed capacitance information for the net. Entries in the *CAP section come in two forms, one for a capacitor lumped to ground and one for a coupled capacitor.

A capacitor lumped to ground has three fields,

– an identifying integer,

– a node name and

– the capacitance value of this node

– e.g

o 1 regcontrol_top/GRC/U9743:E 0.936057

A coupling capacitor has four fields,

– an identifying integer,

– two node names and

– The values of the coupling capacitor between these two nodes

– E.g

o 2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675

If netA is coupled to netB, the coupling capacitor will be listed in each net's *CAP section.

*RES Section

The *RES section provides the resistance network for the net.

Entries in *RES section contain 4 fields,

– an identifying integer,

– two node names and

– the resistance between these two nodes.

– E.g

o 1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916

The resistance network for a net can be very complex. SPEF can contain resistor loops or seemingly ridiculously huge resistors even if the layout is a simple point to point route. This is due how the extraction tool cuts nets into tiny pieces for extraction and then mathematically stitches them back together when writing SPEF.

Parasitic Values

The above examples show a single parasitic value for each capacitor or resistor. It is up to the parasitic extraction and delay calculation flow to decide which corner this value represents. SPEF also allows for min:typ:max values to be reported:

1 regcontrol_top/GRC/U9743:E 0.936057:1.02342:1.31343

The IEEE standard requires either 1 or 3 values to be reported. However, some tools will report min:max pairs and it is expected that tools may report many corners (corner1:corner2:corner3:corner4) in the future.

Source : http://vlsi-expert.blogspot.com/2010/08/how-to-read-spef.html

Filler Cells and Decap Cells

Filler Cells:

Filling 100% of the area with regular cells are generally impossible. We need spaces to improve the placement and routing. Once we complete the routing & achieve the timing closure, we may need to fill the empty spaces with filler cells for the following purpose.

• To reduce the DRC Violations created by the base(NWell, PPlus & NPlus) layers.

• Power Rail connection continuity.

Filler Cells doesn't have functionality. They have power rails, Nwell, PPlus and NPlus layers only. If we want to do any ECO's, then the filler cells can be deleted and the empty spaces can be utilized.

Decap Cells:

Clock Latency and Clock Uncertainty

Clock Latency:

• It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin.
• This is a delay specified by the user - not a real, measured thing.

Clock Uncertainty:

In ideal mode the clock signal can arrive at all clock pins simultaneously, but in real world that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty.

For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.

A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:

• The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
  

• The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.

• Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

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Spare Cells

Spare Cells:

• Spare cells are nothing but the Standard Cells.
  
• These cells are placed randomly across the chip for later use.
• Whenever we need to perform some functional ECO's, the spare cells will be used.
• If any bugs reported after the tape-out, we can use these spare cells to fix the bugs.
• The key in having spare cells in your design is that you only need to change the metal layers in order to rewire the logic and fix any bugs. This means you only need to pay for new metal masks, thus SAVING MONEY.
  
• It is basically reduces the cost required to prepare the masks during fabrication as only we need to change the metal layers.
• After a 1.0 tape-out, a 1.1 tape-out means you only changed some metal layers while 2.0 tape-out means you changed your base layers as well.
• These cells can be added by both RTL Designer and Physical Design Engineer based on their project requirement.
• The Spare Cell Input pins must be tied to VSS and Output pins left floating.
  

Please have a look at the following page for more info on spare cells.

http://asicdigitaldesign.wordpress.com/2007/11/26/spare-cells

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Timing Analysis - Part 5

Data Path Types:

The first step for performing Timing Analysis is to break the design into a set of Timing Paths. Each Path has a start-point and end-point.

• The start-point of a path is a clock pin of a sequential element or possibly an input port of the design (The input data can be launched from some external source ).
  

• The end-point of a path is a data input of a sequential element or possibly an output port of the design (The output data can be captured by some external work).
  

The data paths can be divided into 4 types.

• Primary Input - to - Register Path.

• Register - to - Register Path.

• Register - to - Primary Output Path.

• Primary Input - to - Primary Output Path.

Primary Input - to - Register Path:

• Delays off-chip + Combinational logic delays up to the first sequential device.

Register - to - Register Path:

• Delay and timing constraint(Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times.

Register - to - Primary Output Path:

• Starts at a Sequential device.

• CLK-to-Q transition delay + Combinational logic delay + external delay requirements.

Primary Input - to - Primary Output Path:

• Delays off-chip + Combinational logic delays + external delay requirements.

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Timing Analysis - Part 4

Some more commonly used terms in Timing Analysis.

False Path:

• False paths are paths in a design which are functionally never be true.
• A path which has no functional purpose or a path which does not need to be timing constrained.
  
• Paths that are physically exists in the design, but they are not logical/functional paths. These paths are never get sensitized under any input conditions.

Example :

There are 4 timing paths present in the above circuit. They are

• Path 1 -> (A-C-C1-C2-Out)
• Path 2 -> (A-C-Out)
  
• Path 3 -> (B-B1-B2-C-C1-C2-Out)
  
• Path 4 -> (B-B1-B2-C-Out)

Only Path 1 and Path 4 in the above are valid logic paths as select line for the 2 muxes are the same.

MultiCycle Path:

• Multicycle paths are paths which intentionally require more than one clock cycle to propagate the data.

Divided Clock:

• A Clock divider circuit generates a new clock signal with a lower frequency than the original clock signal.

Gated Clock:

• A Gated Clock signal occurs when the clock network contains logic other than inverters and buffers.

Timing Analysis - Part 3

The following are the commonly used terms in Timing Analysis.

Clock Signal:

• A signal used to synchronize the operations of an electronic system. Clock pulses are continuous, precisely spaced changes in voltage.

• The circuit in a digital computer that provides a common reference train of electronic pulses for all other circuits

Pulse Width:

• It is the time between the active and inactive states of the same signal. The register may not latch the data correctly if clocked with a smaller pulse.
  

Setup Time and Hold Time:

• The Setup Time is the time interval before the active clock edge during which the data should remain unchanged.

• The Hold Time is the time interval after the active clock edge during which the data should remain unchanged..
  

Recovery Time and Removal Time :

• It is the time available between the asynchronous signal going inactive to the active clock edge. ( Like setup time for asynchronous port [set, reset] ).

• It is the time available between active clock edge and asynchronous signal going inactive. (Like Hold time for asynchronous port [set, reset] ).

Clock Skew:

• The maximum difference in arrival time of the clock signal to each register in the design.

Input Arrival Time:

• An arrival time defines the time interval during which a data signal arrive at an input ports/pin.

Output Required Time:

• An required time defines the data required time on output ports/pins.

Slack:

• It is the difference between the required time and the arrival time.

• Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met.

• Slack analysis is used to identify the timing critical paths in a design.

Critical Path:

• Any logical path in the design that violates the timing constraints/path with a negative slack.

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