Filler Cells and Decap Cells

Filler Cells:

Filling 100% of the area with regular cells are generally impossible. We need spaces to improve the placement and routing. Once we complete the routing & achieve the timing closure, we may need to fill the empty spaces with filler cells for the following purpose.

• To reduce the DRC Violations created by the base(NWell, PPlus & NPlus) layers.

• Power Rail connection continuity.

Filler Cells doesn't have functionality. They have power rails, Nwell, PPlus and NPlus layers only. If we want to do any ECO's, then the filler cells can be deleted and the empty spaces can be utilized.

Decap Cells:

Clock Latency and Clock Uncertainty

Clock Latency:

• It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin.
• This is a delay specified by the user - not a real, measured thing.

Clock Uncertainty:

In ideal mode the clock signal can arrive at all clock pins simultaneously, but in real world that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty.

For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.

A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:

• The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
  

• The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.

• Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

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Spare Cells

Spare Cells:

• Spare cells are nothing but the Standard Cells.
  
• These cells are placed randomly across the chip for later use.
• Whenever we need to perform some functional ECO's, the spare cells will be used.
• If any bugs reported after the tape-out, we can use these spare cells to fix the bugs.
• The key in having spare cells in your design is that you only need to change the metal layers in order to rewire the logic and fix any bugs. This means you only need to pay for new metal masks, thus SAVING MONEY.
  
• It is basically reduces the cost required to prepare the masks during fabrication as only we need to change the metal layers.
• After a 1.0 tape-out, a 1.1 tape-out means you only changed some metal layers while 2.0 tape-out means you changed your base layers as well.
• These cells can be added by both RTL Designer and Physical Design Engineer based on their project requirement.
• The Spare Cell Input pins must be tied to VSS and Output pins left floating.
  

Please have a look at the following page for more info on spare cells.

http://asicdigitaldesign.wordpress.com/2007/11/26/spare-cells

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Timing Analysis - Part 5

Data Path Types:

The first step for performing Timing Analysis is to break the design into a set of Timing Paths. Each Path has a start-point and end-point.

• The start-point of a path is a clock pin of a sequential element or possibly an input port of the design (The input data can be launched from some external source ).
  

• The end-point of a path is a data input of a sequential element or possibly an output port of the design (The output data can be captured by some external work).
  

The data paths can be divided into 4 types.

• Primary Input - to - Register Path.

• Register - to - Register Path.

• Register - to - Primary Output Path.

• Primary Input - to - Primary Output Path.

Primary Input - to - Register Path:

• Delays off-chip + Combinational logic delays up to the first sequential device.

Register - to - Register Path:

• Delay and timing constraint(Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times.

Register - to - Primary Output Path:

• Starts at a Sequential device.

• CLK-to-Q transition delay + Combinational logic delay + external delay requirements.

Primary Input - to - Primary Output Path:

• Delays off-chip + Combinational logic delays + external delay requirements.

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Timing Analysis - Part 4

Some more commonly used terms in Timing Analysis.

False Path:

• False paths are paths in a design which are functionally never be true.
• A path which has no functional purpose or a path which does not need to be timing constrained.
  
• Paths that are physically exists in the design, but they are not logical/functional paths. These paths are never get sensitized under any input conditions.

Example :

There are 4 timing paths present in the above circuit. They are

• Path 1 -> (A-C-C1-C2-Out)
• Path 2 -> (A-C-Out)
  
• Path 3 -> (B-B1-B2-C-C1-C2-Out)
  
• Path 4 -> (B-B1-B2-C-Out)

Only Path 1 and Path 4 in the above are valid logic paths as select line for the 2 muxes are the same.

MultiCycle Path:

• Multicycle paths are paths which intentionally require more than one clock cycle to propagate the data.

Divided Clock:

• A Clock divider circuit generates a new clock signal with a lower frequency than the original clock signal.

Gated Clock:

• A Gated Clock signal occurs when the clock network contains logic other than inverters and buffers.

Timing Analysis - Part 3

The following are the commonly used terms in Timing Analysis.

Clock Signal:

• A signal used to synchronize the operations of an electronic system. Clock pulses are continuous, precisely spaced changes in voltage.

• The circuit in a digital computer that provides a common reference train of electronic pulses for all other circuits

Pulse Width:

• It is the time between the active and inactive states of the same signal. The register may not latch the data correctly if clocked with a smaller pulse.
  

Setup Time and Hold Time:

• The Setup Time is the time interval before the active clock edge during which the data should remain unchanged.

• The Hold Time is the time interval after the active clock edge during which the data should remain unchanged..
  

Recovery Time and Removal Time :

• It is the time available between the asynchronous signal going inactive to the active clock edge. ( Like setup time for asynchronous port [set, reset] ).

• It is the time available between active clock edge and asynchronous signal going inactive. (Like Hold time for asynchronous port [set, reset] ).

Clock Skew:

• The maximum difference in arrival time of the clock signal to each register in the design.

Input Arrival Time:

• An arrival time defines the time interval during which a data signal arrive at an input ports/pin.

Output Required Time:

• An required time defines the data required time on output ports/pins.

Slack:

• It is the difference between the required time and the arrival time.

• Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met.

• Slack analysis is used to identify the timing critical paths in a design.

Critical Path:

• Any logical path in the design that violates the timing constraints/path with a negative slack.

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Timing Analysis - Part 2

What is Dynamic Timing Analysis?.

Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulation vectors cannot guarantee the 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Advantages:

• More Accurate than Static Timing Analysis.
• Uses the same test stimulus as Logic Simulation.
• Evaluates worst-case timing using both minimum and maximum delay.
  
• Best Method to Analyze the Asynchronous Circuits.
• Does not report false errors.
  

Limitations:

• Requires an exhaustive set of input test vectors.
• It is not path oriented.
  
• Slow when compared to STA as it checks the functionality of the design.
• It requires functional behavioral models.
  
• Requires more memory and CPU resources than STA.

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Timing Analysis - Part 1

What is Static Timing Analysis?.

There are so many definitions available for Static Timing Analysis and I have captured few of them below.

• Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.

• Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

• STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

Advantages:

• It is path oriented and finds all setup and hold violations.
• Much faster than timing-driven and gate-level Simulation.
• Exhaustive in nature.
• Circuit functionality is not checked.
• Does not required any input vectors for the analysis.

Limitations:

• Works best with Synchronous circuits.
• Complex to learn.
  
• Must define timing requirements and exceptions.
• It can report false errors.
• It cannot detect timing errors related to logical operation.
  
• Difficulty in handling with Multiple Clocks, False Paths, Latches and Multicycle Paths.