Timing Analysis - Part 4

Some more commonly used terms in Timing Analysis.

False Path:

• False paths are paths in a design which are functionally never be true.
• A path which has no functional purpose or a path which does not need to be timing constrained.
  
• Paths that are physically exists in the design, but they are not logical/functional paths. These paths are never get sensitized under any input conditions.

Example :

There are 4 timing paths present in the above circuit. They are

• Path 1 -> (A-C-C1-C2-Out)
• Path 2 -> (A-C-Out)
  
• Path 3 -> (B-B1-B2-C-C1-C2-Out)
  
• Path 4 -> (B-B1-B2-C-Out)

Only Path 1 and Path 4 in the above are valid logic paths as select line for the 2 muxes are the same.

MultiCycle Path:

• Multicycle paths are paths which intentionally require more than one clock cycle to propagate the data.

Divided Clock:

• A Clock divider circuit generates a new clock signal with a lower frequency than the original clock signal.

Gated Clock:

• A Gated Clock signal occurs when the clock network contains logic other than inverters and buffers.

Timing Analysis - Part 3

The following are the commonly used terms in Timing Analysis.

Clock Signal:

• A signal used to synchronize the operations of an electronic system. Clock pulses are continuous, precisely spaced changes in voltage.

• The circuit in a digital computer that provides a common reference train of electronic pulses for all other circuits

Pulse Width:

• It is the time between the active and inactive states of the same signal. The register may not latch the data correctly if clocked with a smaller pulse.
  

Setup Time and Hold Time:

• The Setup Time is the time interval before the active clock edge during which the data should remain unchanged.

• The Hold Time is the time interval after the active clock edge during which the data should remain unchanged..
  

Recovery Time and Removal Time :

• It is the time available between the asynchronous signal going inactive to the active clock edge. ( Like setup time for asynchronous port [set, reset] ).

• It is the time available between active clock edge and asynchronous signal going inactive. (Like Hold time for asynchronous port [set, reset] ).

Clock Skew:

• The maximum difference in arrival time of the clock signal to each register in the design.

Input Arrival Time:

• An arrival time defines the time interval during which a data signal arrive at an input ports/pin.

Output Required Time:

• An required time defines the data required time on output ports/pins.

Slack:

• It is the difference between the required time and the arrival time.

• Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met.

• Slack analysis is used to identify the timing critical paths in a design.

Critical Path:

• Any logical path in the design that violates the timing constraints/path with a negative slack.

.

Timing Analysis - Part 2

What is Dynamic Timing Analysis?.

Dynamic timing analysis uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations. The problem is that the simulation vectors cannot guarantee the 100% coverage. Dynamic timing simulation is still preferred for non-synchronous logic style. As a rule, however, only dynamic timing verification tools support glitch detection and race conditions, since these are inherently dynamic events.

Advantages:

• More Accurate than Static Timing Analysis.
• Uses the same test stimulus as Logic Simulation.
• Evaluates worst-case timing using both minimum and maximum delay.
  
• Best Method to Analyze the Asynchronous Circuits.
• Does not report false errors.
  

Limitations:

• Requires an exhaustive set of input test vectors.
• It is not path oriented.
  
• Slow when compared to STA as it checks the functionality of the design.
• It requires functional behavioral models.
  
• Requires more memory and CPU resources than STA.

.

Timing Analysis - Part 1

What is Static Timing Analysis?.

There are so many definitions available for Static Timing Analysis and I have captured few of them below.

• Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.

• Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.

• STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

Advantages:

• It is path oriented and finds all setup and hold violations.
• Much faster than timing-driven and gate-level Simulation.
• Exhaustive in nature.
• Circuit functionality is not checked.
• Does not required any input vectors for the analysis.

Limitations:

• Works best with Synchronous circuits.
• Complex to learn.
  
• Must define timing requirements and exceptions.
• It can report false errors.
• It cannot detect timing errors related to logical operation.
  
• Difficulty in handling with Multiple Clocks, False Paths, Latches and Multicycle Paths.